To modify and advance the knowledge of VLSI design (using VHDL language), which is the future of all compressed technologies.

The event consists of two rounds. Each round has a prescribed set of rules which has to be followed by the participants.

Round I will be divided into 3 sets of 12 objective type questions each of a particular set pattern.

Selected students from the previous round will have to go through basic VHDL programming and will have to sort out the programming error and run it in Round II.

Rounds:

Round I:

Objective type questions and basics of VHDL programming.

Round II:

Troubleshooting/ Modeling of Digital Systems under the given constraints.

• Round I: (Time – 20 min approx)
• Time based objective test with negative marking.
• Minimum cut off has to be cleared (cut off to be decided).
• Round II: (Time – 1 hour approx)
• Questions will be distributed on lottery system.
• Time based test.
• Depending on the number of candidates, a particular section of students completing first will be selected.

Event Co-ordinators

Aniruddha K. Bordoloi

+91-9837739459

Manish Jha

+91-9719329345

All queries should be redirected to:

fermions@techinnovate.org